Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...
EDN

A short course on SystemVerilog classes for UVM verification

Learning any language can be difficult when so many words take on different meanings in different contexts. “Why does a farmer produce produce?” These homonyms can be confusing even for native ...
EDN

Getting in sync with UVM sequences

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...
Yahoo

EVE's ZeBu SystemVerilog Approach Used by Fujitsu Kyusyu Network Technologies to Implement UVM Co-Emulation

SAN JOSE, CA--(Marketwire -09/04/12)- EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
Semiconductor Engineering

Extending UVM To Analog

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...